Modern accelerator facilities require deterministic timing distribution, sub-nanosecond synchronization, and ultra-fast protection mechanisms to guarantee safe and coordinated operation across RF systems, diagnostics, and beam transport. White Rabbit (WR) technology has demonstrated exceptional performance in timing accuracy, but its integration into a complete timing and protection infrastructure suitable for industrial-grade operation remains an open challenge. This contribution presents a new architecture that unifies WR-based timing, trigger generation, event distribution, and machine protection into a single, coherent system. The proposed design introduces synchronous trigger/gate engines, deterministic event sequencing, WR-referenced RF timing, and a low-latency interlock propagation mechanism capable of reacting within a few microseconds. We describe the hardware and firmware concepts, integration with standard control frameworks (EPICS), signal distribution strategies, and expected performance in multi-node networks. Results from initial prototyping and system-level integration show how WR can serve simultaneously as the global timing backbone and as the transport layer for distributed machine protection. This work demonstrates a scalable approach suitable for future fusion, accelerator-driven, and high-intensity proton facilities.

This work presents the hardware design and performance evaluation of a new Low-Level Radio Frequency (LLRF) system developed for the ALBA synchrotron, operating at the third harmonic frequency of 1.5 GHz. The system is implemented on a MicroTCA (uTCA) platform and is composed of a Rear Transition Module (RTM) that performs the analog front-end processing and down-conversion to an intermediate frequency, together with an Advanced Mezzanine Card (AMC) that digitizes the RF signals at high speed and provides all digital interfaces required by the control system. The hardware platform supplies all necessary resources for the ALBA firmware team to instantiate their own DSP algorithms, feedback loops, synchronization blocks, and machine-specific control strategies, ensuring full flexibility for future developments. This work describes in detail the architecture of the designed hardware, including clock distribution, signal conditioning, conversion stages, digital interfaces, and integration within the uTCA ecosystem. Experimental results are presented both from laboratory characterization and from commissioning tests performed at the ALBA synchrotron. These results demonstrate that the system meets the required performance in terms of stability, noise, linearity, dynamic range, and timing accuracy, validating the suitability of the developed LLRF hardware for high-precision accelerator operation.